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W9425G6JH 4 m 4 banks 16 bits ddr sdram publication release date: may 26, 2010 - 1 - revision a01 table of contents- 1. general des cription............................................................................................................ .................4 2. features ....................................................................................................................... .............................4 3. key paramet ers ................................................................................................................. .....................5 4. pin configu ration .............................................................................................................. ....................6 5. pin des cription................................................................................................................ ........................7 6. block di agram .................................................................................................................. .......................8 7. functional d escript ion......................................................................................................... ..............9 7.1 power up sequenc e .............................................................................................................. ............9 7.2 command fu nction ............................................................................................................... ...........10 7.2.1 bank activate comma nd ......................................................................................................10 7.2.2 bank precharg e comma nd ..................................................................................................10 7.2.3 precharge all command ......................................................................................................10 7.2.4 write co mmand .................................................................................................................. .10 7.2.5 write with auto-p recharge co mmand...................................................................................10 7.2.6 read co mmand ................................................................................................................... 10 7.2.7 read with auto-pre charge co mmand ..................................................................................10 7.2.8 mode register set comma nd ..............................................................................................11 7.2.9 extended mode regist er set co mmand ..............................................................................11 7.2.10 no-operation command ......................................................................................................11 7.2.11 burst read stop command..................................................................................................11 7.2.12 device desele ct comm and ..................................................................................................11 7.2.13 auto refres h comma nd .......................................................................................................11 7.2.14 self refresh en try comm and...............................................................................................12 7.2.15 self refresh ex it comm and .................................................................................................12 7.2.16 data write enable /disable command .................................................................................12 7.3 read oper ation ................................................................................................................. ...............12 7.4 write oper ation ................................................................................................................ ................13 7.5 prechar ge...................................................................................................................... ...................13 7.6 burst termi nation .............................................................................................................. ...............13 7.7 refresh o peration .............................................................................................................. ..............13 7.8 power down mode ................................................................................................................ ...........14 7.9 input clock frequency change duri ng precharge powe r down mode ............................................14 7.10 mode register operat ion ........................................................................................................ .........14 7.10.1 burst length field (a2 to a0) ................................................................................................14 7.10.2 addressing mode se lect (a 3)...............................................................................................15 www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 2 - revision a01 7.10.3 cas latency field (a6 to a4)................................................................................................16 7.10.4 dll reset bit (a 8) ............................................................................................................. ...16 7.10.5 mode register /extended mode regi ster change bits (ba0, ba1) ........................................16 7.10.6 extended mode regi ster fi eld ..............................................................................................16 7.10.7 reserved field ................................................................................................................. .....16 8. operation mode ................................................................................................................. ...................17 8.1 simplified tr uth t able ......................................................................................................... .............17 8.2 function trut h tabl e ........................................................................................................... .............18 8.3 function truth t able for cke................................................................................................... ........21 8.4 simplified st ated dia gram ...................................................................................................... ..........22 9. electrical cha racteris tics ..................................................................................................... .......23 9.1 absolute maxi mum ra tings ....................................................................................................... .......23 9.2 recommended dc operat ing condit ions ........................................................................................23 9.3 capacit ance .................................................................................................................... .................24 9.4 leakage and output buffe r characte ristics...................................................................................... 24 9.5 dc characte ristics ............................................................................................................. ..............25 9.6 ac characteristics and o perating cond ition ....................................................................................2 6 9.7 ac test conditi ons ............................................................................................................. .............27 10. system characteristics for ddr s dram.....................................................................................29 10.1 table 1: input slew rate for dq, dq s, and dm ..............................................................................29 10.2 table 2: input setup & hold ti me derating for slew ra te ...............................................................29 10.3 table 3: input/output setup & hold time derating fo r slew rate....................................................29 10.4 table 4: input/output setup & hold dera ting for rise/fall de lta slew rate ....................................29 10.5 table 5: output slew rate char acteristics (x16 de vices only)........................................................29 10.6 table 6: output slew rate ma tching ratio char acterist ics ..............................................................30 10.7 table 7: ac overshoot/undershoot specif ication for address and control pins ..............................30 10.8 table 8: overshoot/undershoot specific ation for data, str obe, and mask pins...............................31 10.9 system notes: .................................................................................................................. ................32 11. timing w aveforms ............................................................................................................... .................34 11.1 command inpu t timing ........................................................................................................... .........34 11.2 timing of the clk sign als ...................................................................................................... ..........34 11.3 read timing (bur st length = 4) ................................................................................................. ......35 11.4 write timing (bur st length = 4) ................................................................................................ .......36 11.5 dm, data mask (w9425g6j h) .....................................................................................................3 7 11.6 mode register se t (mrs) timing................................................................................................. ....38 11.7 extend mode register set (emrs) timing ......................................................................................39 11.8 auto-precharge timing (r ead cycle, cl = 2) ..................................................................................40 11.9 auto-precharge timing (read cy cle, cl = 2), continue d..................................................................41 11.10 auto-precharge timi ng (write cycle) ............................................................................................ ...42 www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 3 - revision a01 11.11 read interrupted by read (cl = 2, bl = 2, 4, 8)..............................................................................43 11.12 burst read stop (bl = 8) ....................................................................................................... ..........43 11.13 read interrupted by wr ite & bst (bl = 8) ....................................................................................... 44 11.14 read interrupted by pr echarge (b l = 8) ......................................................................................... .44 11.15 write interrupted by wr ite (bl = 2, 4, 8)...................................................................................... .....45 11.16 write interrupted by re ad (cl = 2, bl = 8)..................................................................................... .45 11.17 write interrupted by re ad (cl = 3, bl = 4)..................................................................................... .46 11.18 write interrupted by precharge (bl = 8)........................................................................................ ...46 11.19 2 bank interleave read oper ation (cl = 2, bl = 2)......................................................................... 47 11.20 2 bank interleave read oper ation (cl = 2, bl = 4)......................................................................... 47 11.21 4 bank interleave read oper ation (cl = 2, bl = 2)......................................................................... 48 11.22 4 bank interleave read oper ation (cl = 2, bl = 4)......................................................................... 48 11.23 auto refres h cycle ............................................................................................................. .............49 11.24 precharged/active power down mo de entry and ex it timi ng ..........................................................49 11.25 input clock frequency chan ge during precharge powe r down mode timi ng.................................49 11.26 self refresh entry and exit timing............................................................................................. ......50 12. package specif ication .......................................................................................................... .............51 12.1 tsop 66 li ? 400 mi l ........................................................................................................... .............51 13. revision history ............................................................................................................... ....................52 www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 4 - revision a01 1. general description W9425G6JH is a cmos double data rate synchronous dynamic random access memory (ddr sdram), organized as 4,194,304 words 4 banks 16 bits. W9425G6JH delivers a data bandwidth of up to 500m words per second (-4). to fully comply with the personal computer industrial standard, W9425G6JH is sorted into the following speed grades: -4, -5 and -5i. the -4 is compliant to the ddr500/cl3 and cl4 specification. t he -5/-5i is compliant to the ddr400/cl3 specification (the -5i grade which is guaranteed to support -40c ~ 85c). all input reference to the positive edge of clk (except for dq, dm and cke). the timing reference point for the differential clock is when the clk and clk signals cross during a transition. write and read data are synchronized with the both edges of dqs (data strobe). by having a programmable mode r egister, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W9425G6JH is ideal for main memory in high performance applications. 2. features ? 2.5v 0.2v power supply for ddr400 ? 2.4v~2.7v power supply for ddr500 ? up to 250 mhz clock frequency ? double data rate architecture; two data transfers per clock cycle ? differential clock inputs (clk and clk ) ? dqs is edge-aligned with data for read; center-aligned with data for write ? cas latency: 2, 2.5, 3 and 4 ? burst length: 2, 4 and 8 ? auto refresh and self refresh ? precharged power down and active power down ? write data mask ? write latency = 1 ? 7.8s refresh interval (8k/64 ms refresh) ? maximum burst refresh cycle: 8 ? interface: sstl_2 ? packaged in tsop ii 66-pin, using lead free materials with rohs compliant www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 5 - revision a01 3. key parameters symbol description min/max. -4 -5/-5i min. - 7.5 ns cl = 2 max. - 12 ns min. - 6 ns cl = 2.5 max. - 12 ns min. 4 ns 5 ns cl = 3 max. 12 ns 12 ns min. 4 ns - t ck clock cycle time cl = 4 max. 12 ns - t ras active to precharge command period min. 36 ns 40 ns t rc active to ref/active command period min. 52 ns 55 ns i dd0 operating current: one bank acti ve-precharge max. 75 ma 65 ma i dd1 operating current: one bank active -read-precharge max. 90 ma 80 ma i dd4r burst operation current max. 140 ma 120 ma i dd4w burst operation current max. 135 ma 115 ma i dd5 auto refresh burst current max. 70 ma 65 ma i dd6 self-refresh current max. 2 ma 2 ma www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 6 - revision a01 4. pin configuration v ss dq15 v ssq dq14 dq13 v ddq dq12 dq11 v ssq dq10 dq9 v ddq dq8 v ss nc udqs clk cke a11 a9 a8 a7 a6 a5 a4 v ss 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 v dd dq0 v ddq dq1 dq2 v ssq dq3 dq4 v ddq dq5 dq6 v ssq dq7 nc v ddq ba0 ba1 a10/ap a0 a1 a2 a3 cs ras cas we 28 29 30 31 32 33 39 38 37 36 35 34 v dd ldm nc ldqs nc v dd nc v ssq nc a12 nc clk udm v ref www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 7 - revision a01 5. pin description pin number pin name function description 28 ? 32, 35 ? 42 a0 ? a12 address multiplexed pins for row and column address. row address: a0 ? a12. column address: a0 ? a8. (a10 is used for auto-precharge) 26, 27 ba0, ba1 bank select select bank to activate during row address latch time, or bank to read/write during column address latch time. 2, 4, 5, 7, 8, 10, 11, 13, 54, 56, 57, 59, 60, 62, 63, 65 dq0 ? dq15 data input/ output the dq0 ? dq15 input and out put data are synchronized with both edges of dqs. 16,51 ldqs, udqs data strobe dqs is bi-directional signal. dqs is input signal during write operation and output signal duri ng read operation. it is edge- aligned with read data, center-aligned with write data. 24 cs chip select disable or enable the command decoder. when command decoder is disabled, new command is ignored and previous operation continues. 23, 22, 21 ras , cas , we command inputs command inputs (along with cs ) define the command being entered. 20, 47 ldm, udm write mask when dm is asserted ?high? in burst write, the input data is masked. dm is synchronized with both edges of dqs. 45, 46 clk, clk differential clock inputs all address and control input signals are sampled on the crossing of the positive edge of clk and negative edge of clk . 44 cke clock enable cke controls the clock activation and deactivation. when cke is low, power down mode, suspend mode, or self refresh mode is entered. 49 v ref reference voltage v ref is reference voltage for inputs. 1, 18, 33 v dd power power for logic circuit inside ddr sdram. 34, 48, 66 v ss ground ground for logic circuit inside ddr sdram. 3, 9, 15, 55, 61 v ddq power for i/o buffer separated power from v dd , used for output buffer, to improve noise. 6, 12, 52, 58, 64 v ssq ground for i/o buffer separated ground from v ss , used for output buffer, to improve noise. 14, 17, 19, 25, 43, 50, 53 nc no connection no connection www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 8 - revision a01 6. block diagram cke a10 dll clock buffer command decoder address buffer refresh counter column counter control signal generator mode register column decoder sense amplifier cell array bank #2 column decoder sense amplifier cell array bank #0 column decoder sense amplifier cell array bank #3 data control circuit dq buffer column decoder sense amplifier cell array bank #1 note: the cell array configuration is 8192 * 512 * 16 row decoder row decoder row decoder row decoder a0 a9 a11 a12 ba1 ba0 cs ras cas we clk clk dq0 dq15 prefetch register ldm udm udqs ldqs www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 9 - revision a01 7. functional description 7.1 power up sequence (1) apply power and attempt to cke at a low state ( inputs maintain stable for 200 s min. initialization sequence after power-up www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 10 - revision a01 7.2 command function 7.2.1 bank activate command ( ras = "l", cas = "h", we = "h", ba0, ba1 = bank, a0 to a12 = row address) the bank activate command activates the bank designated by the ba (bank address) signal. row addresses are latched on a0 to a12 when this comm and is issued and the cell data is read out of the sense amplifiers. the maximum time that each b ank can be held in the active state is specified as t ras (max) . after this command is issued, read or write operation can be executed. 7.2.2 bank precharge command ( ras = "l", cas = "h", we = "l", ba0, ba1 = bank, a10 = "l ", a0 to a9, a11, a12 = don?t care) the bank precharge command percharges the bank designated by ba. the precharged bank is switched from the active state to the idle state. 7.2.3 precharge all command ( ras = "l", cas = "h", we = "l", ba0, ba1 = don?t care, a10 = "h", a0 to a9, a11, a12 = don?t care) the precharge all command precharges all banks simultaneously. then all banks are switched to the idle state. 7.2.4 write command ( ras = "h", cas = "l", we = "l", ba0, ba1 = bank, a10 = "l ", a0 to a8 = column address) the write command performs a write operation to the bank designated by ba. the write data are latched at both edges of dqs. the length of the write data (burst length) and column access sequence (addressing mode) must be in the mode register at power- up prior to the write operation. 7.2.5 write with auto-precharge command ( ras = "h", cas = "l", we = "l", ba0, ba1 = bank, a10 = "h", a0 to a8 = column address) the write with auto-precharge command performs the precharge operation automatically after the write operation. this command must not be interrupted by any other commands. 7.2.6 read command ( ras = "h", cas = "l", we = "h", ba0, ba1 = bank, a10 = "l ", a0 to a8 = column address) the read command performs a read operation to the bank designated by ba. the read data are synchronized with both edges of dqs. the length of read data (burst length), addressing mode and cas latency (access time from cas command in a clock cycle) must be programmed in the mode register at power-up prior to the read operation. 7.2.7 read with auto-precharge command ( ras = "h", cas = ?l?, we = ?h?, ba0, ba1 = bank, a10 = ?h?, a0 to a8 = column address) the read with auto-precharge command automatic ally performs the precharge operation after the read operation. www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 11 - revision a01 1) reada t ras (min) - (bl/2) x t ck internal precharge operation begins after bl/2 cycle from read with auto-precharge command. 2) t rcd(min) reada < t ras(min) - (bl/2) x t ck data can be read with shortest latency, but the internal precharge operation does not begin until after t ras (min) has completed. this command must not be interrupted by any other command. 7.2.8 mode register set command ( ras = "l", cas = "l", we = "l", ba0 = "l", ba1 = "l", a0 to a12 = register data) the mode register set command programs the va lues of cas latency, addressing mode, burst length and dll reset in the mode register. the default values in the mode register after power- up are undefined, therefore this command must be issued during the power-up sequence. also, this command can be issued while all banks are in t he idle state. refer to the table for specific codes. 7.2.9 extended mode register set command ( ras = "l", cas = "l", we = "l", ba0 = "h", ba1 = "l", a0 to a12 = register data) the extended mode register set command can be implemented as needed for function extensions to the standard (sdr-sdram). these additional functions include dll enable/disable, output drive strength selection. the default val ue of the extended mode register is not defined; therefore this command must be issued during t he power-up sequence for enabling dll. refer to the table for specific codes. 7.2.10 no-operation command ( ras = "h", cas = "h", we = "h") the no-operation command simply performs no operation (same command as device deselect). 7.2.11 burst read stop command ( ras = "h", cas = "h", we = "l") the burst stop command is used to stop the burst operation. this command is only valid during a burst read operation. 7.2.12 device deselect command ( cs = "h") the device deselect command disables the command decoder so that the ras , cas , we and address inputs are ignored. this command is similar to the no-operation command. 7.2.13 auto refresh command ( ras = "l", cas = "l", we = "h", cke = "h", ba0, ba1, a0 to a12 = don?t care) auto refresh is used during normal operation of the ddr sdram and is analogous to cas? before?ras (cbr) refresh in previous dram ty pes. this command is non persistent, so it must be issued each time a refresh is required. the refresh addressing is generated by the inte rnal refresh controller. this makes the address bits ?don?t care? during an auto refresh command. the ddr sdram requires auto www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 12 - revision a01 refresh cycles at an average periodic interval of t refi (maximum). to allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. a maximum of eight auto refresh commands can be posted to any given ddr sdram, and the maximum absolute interv al between any auto refresh command and the next auto refresh command is 8 * t refi . 7.2.14 self refresh entry command ( ras = "l", cas = "l", we = "h", cke = "l", ba0, ba1, a0 to a12 = don?t care) the self refresh command can be used to retain data in the ddr sdram, even if the rest of the system is powered down. when in the se lf refresh mode, the ddr sdram retains data without external clocking. the self refresh command is initiated like an auto refresh command except cke is disabled (low). the dll is automatically disabled upon entering self refresh, and is automatically enabled upon exiting self refresh. any time the dll is enabled a dll reset must follow and 200 clock cycles should occur before a read command can be issued. input signals except cke are ?d on?t care? during self refresh. since cke is a sstl_2 input, v ref must be maintained during self refresh. 7.2.15 self refresh exit command (cke = "h", cs = "h" or cke = "h", ras = "h", cas = "h") the procedure for exiting self refresh requires a sequence of commands. first, clk must be stable prior to cke going back high. once c ke is high, the ddr sdram must have nop commands issued for t xsnr because time is required for the completion of any internal refresh in progress. a simple algorithm for meeting both re fresh and dll requirements is to apply nops for 200 clock cycles before applying any other command. the use of self refreh mode introduces the po ssibility that an internally timed event can be missed when cke is raised for exit from self refresh mode. upon exit from self refresh an extra auto refresh command is recommended. 7.2.16 data write enable /disable command (dm = "l/h" or ldm, udm = "l/h") during a write cycle, the dm or ldm, udm signal functions as data mask and can control every word of the input data. the ldm signal controls dq0 to dq7 and udm signal controls dq8 to dq15. 7.3 read operation issuing the bank activate command to the idle ban k puts it into the active state. when the read command is issued after t rcd from the bank activate command, the data is read out sequentially, synchronized with both edges of dqs (burst read operation). the initial read data becomes available after cas latency from the issuing of the read command. the cas latency must be set in the mode register at power-up. when the precharge operation is performed on a bank during a burst read and operation, the burst operation is terminated. when the read with auto-precharge command is issued, the precharge operation is performed automatically after the read cycle then the bank is switched to the idle state. this command cannot be interrupted by any other commands. refer to the diagrams for read operation. www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 13 - revision a01 7.4 write operation issuing the write command after t rcd from the bank activate command. the input data is latched sequentially, synchronizing with both edges(rising & falling) of dqs after the write command (burst write operation). the bur st length of the write data (b urst length) and addressing mode must be set in the mode register at power-up. when the precharge operation is performed in a bank during a burst write operation, the burst operation is terminated. when the write with auto-precharge command is issued, the precharge operation is performed automatically after the write cycle, then the bank is switched to the id le state, the write with auto- precharge command cannot be interrupted by any other command for the entire burst data duration. refer to the diagrams for write operation. 7.5 precharge there are two commands, which perform t he precharge operation (bank precharge and precharge all). when the bank precharge command is issued to the active bank, the bank is precharged and then switched to the idle state. the bank precharge command can precharge one bank independently of the other bank and hold the unprecharged bank in the active state. the maximum time each bank can be held in the active state is specified as t ras (max) . therefore, each bank must be precharged within t ras(max) from the bank activate command. the precharge all command can be used to prec harge all banks simultaneously. even if banks are not in the active state, the precharge all command can still be issued. in this case, the precharge operation is performed only for t he active bank and the precharge bank is then switched to the idle state. 7.6 burst termination when the precharge command is used for a bank in a burst cycle, the burst operation is terminated. when burst read cycle is interr upted by the precharge command, read operation is disabled after clock cycle of (cas latency) from the precharge command. when the burst write cycle is interrupted by the prechar ge command, the input circuit is re set at the same clock cycle at which the precharge command is issued. in this case, the dm signal must be asserted "high" during t wr to prevent writing the invalided data to the cell array. when the burst read stop command is issued for the bank in a burst read cycle, the burst read operation is terminated. the burst read stop command is not supported during a write burst operation. refer to the diagrams for burst termination. 7.7 refresh operation two types of refresh operation can be performed on the device: auto refresh and self refresh. by repeating the auto refresh cycle, each bank in turn refreshed automatically. the refresh operation must be performed 8192 times (rows) within 64ms. the period between the auto refresh command and the next command is specified by t rfc . self refresh mode enters issuing the self refresh command (cke asserted "low") while all banks are in the idle state. the device is in self refr esh mode for as long as cke held "low". in the case of distributed auto refresh commands, distribut ed auto refresh commands must be issued every 7.8 s and the last distributed auto refresh co mmands must be performed within 7.8 s before entering the self refresh mode. after exiting from the self refresh mode, the refresh operation must be performed within 7.8 s. in self refr esh mode, all input/output buffers are disabled, www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 14 - revision a01 resulting in lower power dissipation (except cke buffer). refer to the diagrams for refresh operation. 7.8 power down mode two types of power down mode can be performed on the device: active standby power down mode and precharge standby power down mode. when the device enters the power down mode, all input/output buffers and dll are disabled resulting in low power dissipation (except cke buffer). power down mode enter asserting cke "low" while t he device is not running a burst cycle. taking cke "high" can exit this mode. when cke goes high, a no operation command must be input at next clk rising edge. refer to the diagrams for power down mode. 7.9 input clock frequency change during precharge power down mode ddr sdram input clock frequency can be changed under following condition: ddr sdram must be in precharged power down mode with cke at logic low level. after a minimum of 2 clocks after cke goes low, the clock frequency may change to any frequency between minimum and maximum operating frequency specified for the particular speed grade. during an input clock frequency change, cke must be held low. once the input clock frequency is changed, a stable clock must be provided to dram before precharge power down mode may be exited. the dll must be reset via emrs after precharge power down exit. an additional mrs command may need to be issued to appropriately set cl etc. after the dll relock time, the dram is ready to operate with new clock frequency. 7.10 mode register operation the mode register is programmed by the m ode register set command (mrs/emrs) when all banks are in the idle state. the data to be set in the mode register is transferred using the a0 to a12 and ba0, ba1 address inputs. the mode register designates the operation mode for the read or write cycle. the register is divided into five filed: (1) burst length field to set the length of burst data (2) addressing mode selected bit to designate the column access sequence in a burst cycle (3) cas latency field to set the assess time in clock cycle (4) dll reset fi eld to reset the dll (5) regular/extended mode register filed to select a type of mrs (reg ular/extended mrs). emrs cycle can be implemented the extended function (dll enable/disable mode). the initial value of the mode register (including emrs) after power up is undefined; therefore the mode register set command must be issued before power operation. 7.10.1 burst length field (a2 to a0) this field specifies the data length for column acce ss using the a2 to a0 pins and sets the burst length to be 2, 4, and 8 words. a2 a1 a0 burst length 0 0 0 reserved 0 0 1 2 words 0 1 0 4 words 0 1 1 8 words 1 x x reserved www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 15 - revision a01 7.10.2 addressing mode select (a3) the addressing mode can be one of two modes; in terleave mode or sequential mode, when the a3 bit is "0", sequential mode is selected. when the a3 bit is "1", interleave mode is selected. both addressing mode support burst length 2, 4, and 8 words. a3 addressing mode 0 sequential 1 interleave 7.10.2.1. addressing sequence of sequential mode a column access is performed by incrementing the column address input to the device. the address is varied by the burst length as the following. addressing sequence of sequential mode data access address burst length data 0 n 2 words (address bits is a0) data 1 n + 1 not carried from a0 to a1 data 2 n + 2 4 words (address bit a0, a1) data 3 n + 3 not carried from a1 to a2 data 4 n + 4 data 5 n + 5 8 words (address bits a2, a1 and a0) data 6 n + 6 not carried from a2 to a3 data 7 n + 7 7.10.2.2. addressing sequence for interleave mode a column access is started from the inputted column address and is performed by interleaving the address bits in the sequence shown as the following. addressing sequence of interleave mode data access address burst length data 0 a8 a7 a6 a5 a4 a3 a2 a1 a0 2 words data 1 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 2 a8 a7 a6 a5 a4 a3 a2 a1 a0 4 words data 3 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 4 a8 a7 a6 a5 a4 a3 a2 a1 a0 8 words data 5 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 6 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 7 a8 a7 a6 a5 a4 a3 a2 a1 a0 www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 16 - revision a01 7.10.3 cas latency field (a6 to a4) this field specifies the number of clock cycles fr om the assertion of the read command to the first data read. the minimum values of cas latency depend on the frequency of clk. a6 a5 a4 cas latency 0 0 0 reserved 0 0 1 reserved 0 1 0 2 0 1 1 3 1 0 0 reserved 1 0 1 reserved 1 1 0 2.5 1 1 1 reserved 7.10.4 dll reset bit (a8) this bit is used to reset dll. when the a8 bit is "1", dll is reset. 7.10.5 mode register /extended mode register change bits (ba0, ba1) these bits are used to select mrs/emrs. ba1 ba0 a12-a0 0 0 regular mrs cycle 0 1 extended mrs cycle 1 x reserved 7.10.6 extended mode register field 1) dll switch field (a0) this bit is used to select dll enable or disable a0 dll 0 enable 1 disable 2) output driver size control field (a6, a1) the 100%, 60% and 30% or matched impedance driver strength are required extended mode register set (emrs) as the following: a6 a1 buffer strength 0 0 100% strength 0 1 60% strength 1 0 reserved 1 1 30% strength 7.10.7 reserved field ? test mode entry bit (a7) this bit is used to enter test mode and must be set to "0" for normal operation. ? reserved bits (a9, a10, a11, a12) these bits are reserved for future operations. they must be set to "0" for normal operation. www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 17 - revision a01 8. operation mode the following table shows the operation commands. 8.1 simplified truth table sym. command device state cken-1 cken dm (4) ba0, ba1 a10 a12, a11, a9-a0 cs ras cas we act bank active idle (3) h x x v v v l l h h pre bank precharge any (3) h x x v l x l l h l prea precharge all any h x x x h x l l h l writ write active (3) h x x v l v l h l l writa write with auto- precharge active (3) h x x v h v l h l l read read active (3) h x x v l v l h l h reada read with auto- precharge active (3) h x x v h v l h l h mrs mode register set idle h x x l, l c c l l l l emrs extended mode register set idle h x x h, l v v l l l l nop no operation any h x x x x x l h h h bst burst read stop active h x x x x x l h h l dsl device deselect any h x x x x x h x x x aref auto refresh idle h h x x x x l l l h self self refresh entry idle h l x x x x l l l h h x x x selex self refresh exit idle (self refresh) l h x x x x l h h x h x x x pd power down mode entry idle/ active (5) h l x x x x l h h x h x x x pdex power down mode exit any (power down) l h x x x x l h h x wde data write enable active h x l x x x x x x x wdd data write disable active h x h x x x x x x x notes : 1. v = valid x = don?t care l = low level h = high level 2. cke n signal is input level when commands are issued. cke n-1 signal is input level one clock cycle before the commands are issued. 3. these are state designated by the ba0, ba1 signals. 4. ldm, udm (W9425G6JH). 5. power down mode can not entry in the burst cycle. www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 18 - revision a01 8.2 function truth table (note 1) current state cs ras cas we address command action notes h x x x x dsl nop l h h x x nop/bst nop l h l h ba, ca, a10 read/reada illegal 3 l h l l ba, ca, a10 writ/writa illegal 3 l l h h ba, ra act row activating l l h l ba, a10 pre/prea nop l l l h x aref/self refresh or self refresh 2 idle l l l l op-code mrs/emrs mode register accessing 2 h x x x x dsl nop l h h x x nop/bst nop l h l h ba, ca, a10 read/reada begin read: determine ap 4 l h l l ba, ca, a10 writ/writa begin write: determine ap 4 l l h h ba, ra act illegal 3 l l h l ba, a10 pre/prea precharge 5 l l l h x aref/self illegal row active l l l l op-code mrs/emrs illegal h x x x x dsl continue burst to end l h h h x nop continue burst to end l h h l x bst burst stop l h l h ba, ca, a10 read/reada term burst, new read: determine ap 6 l h l l ba, ca, a10 writ/writa illegal l l h h ba, ra act illegal 3 l l h l ba, a10 pre/prea term burst, precharging l l l h x aref/self illegal read l l l l op-code mrs/emrs illegal h x x x x dsl continue burst to end l h h h x nop continue burst to end l h h l x bst illegal l h l h ba, ca, a10 read/reada term burst, start read: determine ap 6, 7 l h l l ba, ca, a10 writ/writa term burst, start read: determine ap 6 l l h h ba, ra act illegal 3 l l h l ba, a10 pre/prea term burst, precharging 8 l l l h x aref/self illegal write l l l l op-code mrs/emrs illegal www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 19 - revision a01 function truth table, continued current state cs ras cas we address command action notes h x x x x dsl continue burst to end l h h h x nop continue burst to end l h h l x bst illegal l h l h ba, ca, a10 read/reada illegal l h l l ba, ca, a10 writ/writa illegal 3 l l h h ba, ra act illegal 3 l l h l ba, a10 pre/prea illegal l l l h x aref/self illegal read with auto- precharge l l l l op-code mrs/emrs illegal h x x x x dsl continue burst to end l h h h x nop continue burst to end l h h l x bst illegal l h l h ba, ca, a10 read/reada illegal l h l l ba, ca, a10 writ/writa illegal l l h h ba, ra act illegal 3 l l h l ba, a10 pre/prea illegal 3 l l l h x aref/self illegal write with auto- precharge l l l l op-code mrs/emrs illegal h x x x x dsl nop -> idle after t rp l h h h x nop nop -> idle after t rp l h h l x bst illegal l h l h ba, ca, a10 read/reada illegal 3 l h l l ba, ca, a10 writ/writa illegal 3 l l h h ba, ra act illegal 3 l l h l ba, a10 pre/prea idle after t rp l l l h x aref/self illegal precharging l l l l op-code mrs/emrs illegal h x x x x dsl nop -> row active after t rcd l h h h x nop nop -> row active after t rcd l h h l x bst illegal l h l h ba, ca, a10 read/reada illegal 3 l h l l ba, ca, a10 writ/writa illegal 3 l l h h ba, ra act illegal 3 l l h l ba, a10 pre/prea illegal 3 l l l h x aref/self illegal row activating l l l l op-code mrs/emrs illegal www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 20 - revision a01 function truth table, continued current state cs ras cas we address command action note s h x x x x dsl nop -> row active after t wr l h h h x nop nop -> row active after t wr l h h l x bst illegal l h l h ba, ca, a10 read/reada illegal 3 l h l l ba, ca, a10 writ/writa illegal 3 l l h h ba, ra act illegal 3 l l h l ba, a10 pre/prea illegal 3 l l l h x aref/self illegal write recovering l l l l op-code mrs/emrs illegal h x x x x dsl nop -> enter precharge after t wr l h h h x nop nop -> enter precharge after t wr l h h l x bst illegal l h l h ba, ca, a10 read/reada illegal 3 l h l l ba, ca, a10 writ/writa illegal 3 l l h h ba, ra act illegal 3 l l h l ba, a10 pre/prea illegal 3 l l l h x aref/self illegal write recovering with auto- precharge l l l l op-code mrs/emrs illegal h x x x x dsl nop -> idle after t rc l h h h x nop nop -> idle after t rc l h h l x bst illegal l h l h x read/writ illegal l l h x x act/pre/prea illegal refreshing l l l x x aref/self/mrs/emrs illegal h x x x x dsl nop -> row after t mrd l h h h x nop nop -> row after t mrd l h h l x bst illegal l h l x x read/writ illegal mode register accessing l l x x x act/pre/prea/are f/self/mrs/emrs illegal notes : 1. all entries assume that cke was active (high level) during the preceding clock cycle and the current clock cycle. 2. illegal if any bank is not idle. 3. illegal to bank in specified states; function may be legal in the bank indicat ed by bank address (ba), depending on the state of that bank. 4. illegal if t rcd is not satisfied. 5. illegal if t ras is not satisfied. 6. must satisfy burst interrupt condition. 7. must avoid bus contention, bus turn around, and/or satisfy write recovery requirements. 8. must mask preceding data which don?t satisfy t wr remark: h = high level, l = low level, x = high or low level (don?t care), v = valid data www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 21 - revision a01 8.3 function truth table for cke cke current state n-1 n cs ras cas we address action notes h x x x x x x invalid l h h x x x x exit self refresh -> idle after t xsnr l h l h h x x exit self refresh -> idle after t xsnr l h l h l x x illegal l h l l x x x illegal self refresh l l x x x x x maintain self refresh h x x x x x x invalid l h x x x x x exit power down -> idle after t is power down l l x x x x x maintain power down mode h h x x x x x refer to function truth table h l h x x x x enter power down 2 h l l h h x x enter power down 2 h l l l l h x self refresh 1 h l l h l x x illegal h l l l x x x illegal all banks idle l x x x x x x power down h h x x x x x refer to function truth table h l h x x x x enter power down 3 h l l h h x x enter power down 3 h l l l l h x illegal h l l h l x x illegal h l l l x x x illegal row active l x x x x x x power down any state other than listed above h h x x x x x refer to function truth table notes : 1. self refresh can enter only from the all banks idle state. 2. power down occurs when all banks are idle; this mode is referred to as precharge power down. 3. power down occurs when there is a row active in any bank; this mode is referred to as active power down. remark: h = high level, l = low level, x = high or low level (don?t care), v = valid data www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 22 - revision a01 8.4 simplified stated diagram power applied automatic sequence command sequence read a write read row active power down idle mode register set auto refresh self refresh read read a write write a pre charge power on mrs/emrs aref sref srefx pd pdex act bst read write write a write a read a pre pre pre pre active powerdown pd pdex read read a www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 23 - revision a01 9. electrical characteristics 9.1 absolute maximum ratings parameter symbol rating unit input/output voltage v in, v out -0.5 ~ v ddq + 0.5 v power supply voltage v dd, v ddq -1 ~ 3.6 v operating temperature (-4/-5) t opr 0 ~ 70 c operating temperature (-5i) t opr -40 ~ 85 c storage temperature t stg -55 ~ 150 c soldering temperature (10s) t solder 260 c power dissipation p d 1 w short circuit output current i out 50 ma note: stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any ot her conditions above those indicate d in the operational sections of this specification is not implied. exposure to absolute maximum rating condit ions for extended periods may affect reliability. 9.2 recommended dc operating conditions (t a = 0 to 70 c for -4/-5, t a = -40 to 85 c for -5i) sym. parameter min. typ. max. unit notes v dd power supply voltage (for -5/-5i) 2.3 2.5 2.7 v 2 v dd power supply voltage (for -4) 2.4 - 2.7 v 2 v ddq i/o buffer supply voltage (for -5/-5i) 2.3 2.5 2.7 v 2 v ddq i/o buffer supply voltage (for - 4) 2.4 - 2.7 v 2 v ref input reference voltage 0.49 x v ddq 0.50 x v ddq 0.51 x v ddq v 2, 3 v tt termination voltage (system) v ref - 0.04 v ref v ref + 0.04 v 2, 8 v ih (dc) input high voltage (dc) v ref + 0.15 - v ddq + 0.3 v 2 v il (dc) input low voltage (dc) -0.3 - v ref - 0.15 v 2 v ick (dc) differential clock dc input voltage -0.3 - v ddq + 0.3 v 15 v id (dc) input differential voltage. clk and clk inputs (dc) 0.36 - v ddq + 0.6 v 13, 15 v ih (ac) input high voltage (ac) v ref + 0.31 - - v 2 v il (ac) input low voltage (ac) - - v ref - 0.31 v 2 v id (ac) input differential voltage. clk and clk inputs (ac) 0.7 - v ddq + 0.6 v 13, 15 v x (ac) differential ac input cross point voltage v ddq /2 - 0.2 - v ddq /2 + 0.2 v 12, 15 v iso (ac) differential clock ac middle point v ddq /2 - 0.2 - v ddq /2 + 0.2 v 14, 15 notes : undershoot limit: v il (min) = -1.5v with a pulse width < 5 ns overshoot limit: v ih (max) = v ddq +1.5v with a pulse width < 5 ns v ih (dc) and v il (dc) are levels to maintain the current logic state. v ih (ac) and v il (ac) are levels to change to the new logic state. www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 24 - revision a01 9.3 capacitance (v dd = v ddq = 2.5v 0.2v, f = 1 mhz, t a = 25 c, v out (dc) = v ddq /2, v out (peak to peak) = 0.2v) symbol parameter min. max. delta (max.) unit c in input capacitance (except for clk pins) 2.0 3.0 0.5 pf c clk input capacitance (clk pins) 2.0 3.0 0.25 pf c i/o dq, dqs, dm capacit ance 4.0 5.0 0.5 pf note: these parameters are periodically sampled and not 100% tested. 9.4 leakage and output buffer characteristics symbol parameter min. max. unit notes i i (l) input leakage current any input 0v < v in < v dd , v ref pin 0v < v in < 1.35v (all other pins not under test = 0v) -2 2 a i o (l) output leakage current (output disabled, 0v < v out < v ddq ) -5 5 a v oh output high voltage (under ac test load condition) v tt +0.76 - v v ol output low voltage (under ac test load condition) - v tt -0.76 v i oh output levels: full drive option high current (v out = v ddq - 0.373v, min. v ref , min. v tt -15 - ma 4, 6 i ol low current (v out = 0.373v, max. v ref , max. v tt ) 15 - ma 4, 6 i ohr output levels: reduced drive option - 60% high current (v out = v ddq - 0.763v, min. v ref , min. v tt -9 - ma 5 i olr low current (v out = 0.763v, max. vref, max. v tt ) 9 - ma 5 i ohr (30) output levels: reduced drive option - 30% high current (v out = v ddq ? 1.056v, min. v ref , min. v tt -4.5 - ma 5 i olr (30) low current (v out = 1.056v, max. v ref , max. v tt ) 4.5 - ma 5 www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 25 - revision a01 9.5 dc characteristics max. sym. parameter -4 -5/-5i unit notes i dd0 operating current: one bank active-precharge; t rc = t rc min; t ck = t ck min; dq, dm and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles 75 65 7 i dd1 operating current: one bank active-read-precharge; burst = 4; t rc = t rc min; cl = 3; t ck = t ck min; i out = 0 ma; address and control inputs changing once per clock cycle. 90 80 7, 9 i dd2p precharge power down standby current: all banks idle; power down mode; cke < v il max; t ck = t ck min; vin = v ref for dq, dqs and dm 5 5 i dd2n idle standby current: cs > v ih min; all banks idle; cke > v ih min; t ck = t ck min; address and other control inputs changing once per clock cycle; vin > v ih min or vin < v il max for dq, dqs and dm 25 20 7 i dd2f precharge floating standby current: cs > v ih min; all banks idle; cke > v ih min; address and other control inputs changing once per clock cycle; v in = v ref for dq, dqs and dm . 25 20 i dd2q precharge quiet standby current: cs > v ih min; all banks idle; cke > v ih min; address and other control inputs stable at > v ih min or < v il max; vin = v ref for dq, dqs and dm. 20 20 i dd3p active power down standby current: one bank active; power down mode; cke < v il max; t ck = t ck min; vin = v ref for dq, dqs and dm 20 20 ma i dd3n active standby current: cs > v ih min; cke > v ih min; one bank active-precharge; t rc = t ras max; t ck = t ck min; dq, dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle 35 30 7 i dd4r operating current: burst = 2; reads; continuous burst; one bank active; address and control inputs changing once per clock cycle; cl=2; t ck = t ck min; i out = 0ma 140 120 7, 9 i dd4w operating current: burst = 2; write; continuous burst; one bank active; address and control inputs changing once per clock cycle; cl = 2; t ck = t ck min; dq, dm and dqs inputs changing twice per clock cycle 135 115 7 i dd5 auto refresh current: t rc = t rfc min 70 65 7 i dd6 self refresh current: cke < 0.2v ; external clock on; t ck = t ck min 2 2 i dd7 random read current: 4 banks ac tive read with activate every 20ns, auto-precharge read every 20 ns; burst = 4; t rcd = 3; i out = 0ma; dq, dm and dqs inputs changing twice per clock cycle; address changing once per clock cycle 210 175 www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 26 - revision a01 9.6 ac characteristics and operating condition -4 -5/-5i sym. parameter min. max. min. max. unit notes t rc active to ref/active command period 52 55 t rfc ref to ref/active command period 60 70 t ras active to precharge command period 36 70000 40 100000 t rcd active to read/write command delay time 16 15 t rap active to read with auto-precharge enable 16 15 ns t ccd read/write(a) to read/write(b) command period 1 1 t ck t rp precharge to active command period 16 15 t rrd active(a) to active(b) command period 8 10 t wr write recovery time 15 15 ns t dal auto-precharge write recovery + precharge time (t wr /t ck ) + (t rp /t ck ) (t wr /t ck ) + (t rp /t ck ) t ck 18 cl = 2 - - 7.5 12 cl = 2.5 - - 6 12 cl = 3 4 10 5 12 t ck clk cycle time cl = 4 4 10 - - t ac data access time from clk, clk -0.7 0.7 -0.7 0.7 16 t dqsck dqs output access time from clk, clk -0.6 0.6 -0.6 0.6 16 t dqsq data strobe edge to output data edge skew 0.4 0.4 ns t ch clk high level width 0.45 0.55 0.45 0.55 t cl clk low level width 0.45 0.55 0.45 0.55 t ck 11 t hp clk half period (minimum of actual t ch, t cl ) min (t cl ,t ch ) min, (t cl ,t ch ) t qh dq output data hold time from dqs t hp -0.5 t hp -0.5 ns t rpre dqs read preamble time 0.9 1.1 0.9 1.1 t rpst dqs read postamble time 0.4 0.6 0.4 0.6 t ck 11 t ds dq and dm setup time to dqs, slew rate 0.5v/ns 0.4 0.4 t dh dq and dm hold time to dqs, slew rate 0.5v/ns 0.4 0.4 t dipw dq and dm input pulse width (for each input) 1.75 1.75 ns t dqsh dqs input high pulse width 0.35 0.35 t dqsl dqs input low pulse width 0.35 0.35 t dss dqs falling edge to clk setup time 0.2 0.2 t dsh dqs falling edge hold time from clk 0.2 0.2 t ck 11 t wpres clock to dqs write preamble set-up time 0 0 ns t wpre dqs write preamble time 0.25 0.25 t wpst dqs write postamble time 0.4 0.6 0.4 0.6 t dqss write command to first dqs latching transition 0.85 1.15 0.72 1.25 t ck 11 t is input setup time (fast slew rate) 0.6 0.6 19, 21-23 t ih input hold time (fast slew rate) 0.6 0.6 19, 21-23 t is input setup time (slow slew rate) 0.7 0.7 20-23 t ih input hold time (slow slew rate) 0.7 0.7 20-23 t ipw control & address input pulse width (for each input) 2.2 2.2 t hz data-out high-impedance time from clk, clk 0.7 0.7 t lz data-out low-impedance time from clk, clk -0.7 0.7 -0.7 0.7 t t(ss) sstl input transition 0.5 1.5 0.5 1.5 ns t wtr internal write to read command delay 2 2 t ck t xsnr exit self refresh to non-read command 72 75 ns t xsrd exit self refresh to read command 200 200 t ck t refi refresh interval time (4k/ 64ms) 7.8 7.8 s 17 t mrd mode register set cycle time 8 10 ns www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 27 - revision a01 9.7 ac test conditions parameter symbol value unit input high voltage (ac) v ih v ref + 0.31 v input low voltage (ac) v il v ref - 0.31 v input reference voltage v ref 0.5 x v ddq v termination voltage v tt 0.5 x v ddq v differential clock input reference voltage v r v x (ac) v input difference voltage. clk and clk inputs (ac) v id (ac) 1.5 v output timing measurement reference voltage v otr 0.5 x v ddq v v swing (max) v dd q v ss t t v ih min (ac) v ref v il max (ac) slew = (v ih min (ac) - v il max (ac)) / t output 50 vtt timing reference load output v(out) 30pf notes: (1) conditions outside the limits listed under ?absolute maximum ratings? may cause permanent damage to the device. (2) all voltages are referenced to v ss , v ssq. (3) peak to peak ac noise on v ref may not exceed 2% v ref(dc). (4) v oh = 1.95v, v ol = 0.35v (5) v oh = 1.9v, v ol = 0.4v (6) the values of i oh(dc) is based on v ddq = 2.3v and v tt = 1.19v. the values of i ol(dc) is based on v ddq = 2.3v and v tt = 1.11v. (7) these parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of t ck and t rc . (8) v tt is not applied directly to the device. v tt is a system supply for signal termination resistors is expected to be set equal to v ref and must track variations in the dc level of v ref . (9) these parameters depend on the output loading. specified values are obtained with the output open. (10) transition times are measured between v ih min(ac) and v il max(ac) .transition (rise and fall) of input signals have a fixed slope. (11) if the result of nominal calculation with regard to t ck contains more than one decimal place, the result is rounded up to the nearest decimal place. (i.e., t dqss = 1.25 t ck , t ck = 5 ns, 1.25 5 ns = 6.25 ns is rounded up to 6.2 ns.) www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 28 - revision a01 (12) v x is the differential clock cross point voltage where input timing measurement is referenced. (13) v id is magnitude of the difference between clk input level and clk input level. (14) v iso means {v ick (clk)+v ick ( clk )}/2. (15) refer to the figure below. clk clk v ss v ick v x v x v x v x v x v ick v ick v ick v id(ac) v id(ac) 0 v differential v iso v iso(min) v iso(max) v ss (16) t ac and t dqsck depend on the clock jitter. these timing are measured at stable clock. (17) a maximum of eight auto refresh commands can be posted to any given ddr sdram device. (18) t dal = (t wr /t ck ) + (t rp /t ck ) for each of the terms above, if not already an integer, round to the next highest integer. example: for -5 speed grade at cl=2.5 and tck=6 ns t dal = ((15 ns / 6 ns) + (15 ns / 6 ns)) clocks = ((3) + (3)) clocks = 6 clocks (19) for command/address input slew rate 1.0 v/ns. (20) for command/address input slew rate 0.5 v/ns and <1.0 v/ns. (21) for clk & clk slew rate 1.0 v/ns (single--ended). (22) these parameters guaran tee device timing, but they are not necessa rily tested on each device. they may be guaranteed by device design or tester correlation. (23) slew rate is measured between v oh (ac) and v ol (ac). www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 29 - revision a01 10. system characteristics for ddr sdram the following specification parameters are requir ed in systems using ddr500, ddr400 & ddr333 devices to ensure proper system performance. thes e characteristics are fo r system simulation purposes and are guaranteed by design. 10.1 table 1: input slew rate for dq, dqs, and dm ac characteristics sym. ddr500 ddr400 parameter min. max. min. max. unit notes dq/dm/dqs input slew rate measured between vih(dc), vil(dc) and vil(dc), vih(dc) dcslew 0.5 4.0 0.5 4.0 v/ns a, m 10.2 table 2: input setup & hold time derating for slew rate input slew rate t is t ih unit notes 0.5 v/ns 0 0 ps i 0.4 v/ns +50 0 ps i 0.3 v/ns +100 0 ps i 10.3 table 3: input/output setup & hold time derating for slew rate input slew rate t ds t dh unit notes 0.5 v/ns 0 0 ps k 0.4 v/ns +75 0 ps k 0.3 v/ns +150 0 ps k 10.4 table 4: input/output setup & hold derating for rise/fall delta slew rate input slew rate t ds t dh unit notes 0.0 ns/v 0 0 ps j 0.25 ns/v +50 0 ps j 0.5 ns/v +100 0 ps j 10.5 table 5: output slew rate characteristics (x16 devices only) slew rate characteristic typical range (v/ns) minimum (v/ns) maximum (v/ns) notes pullup slew rate 1.2 ~ 2.5 0.7 5.0 a, c, d, f, g, h pulldown slew rate 1.2 ~ 2.5 0.7 5.0 b, c, d, f, g, h www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 30 - revision a01 10.6 table 6: output slew rate matching ratio characteristics slew rate characteristic ddr500 ddr400 parameter min. max. min. max. notes output slew rate matching ratio (pullup to pulldow n) 0.67 1.5 0.67 1.5 e, m 10.7 table 7: ac overshoot/undershoot specification for address and control pins specification parameter ddr500 ddr400 maximum peak amplitude allowed for overshoot 1.5 v 1.5 v maximum peak amplitude allowed for undershoot 1.5 v 1.5 v the area between the overshoot si gnal and vdd must be less than or equal to max. area in figure 3 3.0 v-ns 3.0 v-ns the area between the undershoot si gnal and gnd must be less than or equal to max. area in figure 3 3.0 v-ns 3.0 v-ns 0 0.5 0.68751.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.06.3125 6.5 7.0 -5 -4 -3 -2 -1 0 1 2 3 4 5 max. amplitude = 1.5v overshoot vdd max. area max. amplitude = 1.5v gnd undershoot time (ns) figure 3: address and control ac overshoot and undershoot definition www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 31 - revision a01 10.8 table 8: overshoot/undershoot specifi cation for data, strobe, and mask pins specification parameter ddr500 ddr400 maximum peak amplitude allowed for overshoot 1.2 v 1.2 v maximum peak amplitude allowed for undershoot 1.2 v 1.2 v the area between the overshoot si gnal and vdd must be less than or equal to max. area in figure 4 1.44 v-ns 1.44 v-ns the area between the undershoot si gnal and gnd must be less than or equal to max. area in figure 4 1.44 v-ns 1.44 v-ns 0 0.5 1.0 1.42 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.68 6.0 6.5 7.0 -5 -4 -3 -2 -1 0 1 2 3 4 5 max. amplitude = 1.2v overshoot vdd max. area max. amplitude = 1.2v gnd undershoot time (ns) figure 4: dq/dm/dqs ac overshoot and undershoot definition www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 32 - revision a01 10.9 system notes: a. pullup slew rate is characterized under the test conditions as shown in figure 1. vssq 50 output test point figure 1: pullup slew rate test load b. pulldown slew rate is measured under the test conditions shown in figure 2. vddq 50 output test point figure 2: pulldown slew rate test load c. pullup slew rate is measured between (v ddq /2 - 320 mv 250 mv) pulldown slew rate is measured between (v ddq /2 + 320 mv 250 mv) pullup and pulldown slew rate conditions are to be me t for any pattern of data, including all outputs switching and only one output switching. example: for typical slew rate, dq0 is switching for minimum slew rate, all dq bits are switching worst case pattern for maximum slew rate, only one dq is switchin g from either high to low, or low to high the remaining dq bits remain the same as for previous state d. evaluation conditions typical: 25 o c (t ambient), v ddq = nominal, typical process minimum: 70 o c (t ambient), v ddq = minimum, sl ow-slow process maximum: 0 o c (t ambient), v ddq = maximum, fast-fast process www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 33 - revision a01 e. the ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range. for a given output, it represents the maximum difference between pullup and pulld own drivers due to process variation. f. verified under typical conditions for qualification purposes. g. tsop ii package devices only. h. only intended for operation up to 266 mbps per pin. i. a derating factor will be used to increase t is and t ih in the case where the input slew rate is below 0.5 v/ns as shown in table 2. the input slew ra te is based on the lesser of the slew rates determined by either v ih(ac) to v il(ac) or v ih(dc) to v il(dc) , similarly for rising transitions. j. a derating factor w ill be used to increase t ds and t dh in the case where dq, dm, and dqs slew rates differ, as shown in tables 3 & 4. input slew rate is based on the larger of ac-ac delta rise, fall rate and dc-dc delta rise, fall rate. input slew rate is based on the lesser of the slew rates determined by either v ih(ac) to v il(ac) or v ih(dc) to v il(dc) , similarly for rising transitions. the delta rise/fall rate is calculated as: {1/(slew rate1)}-{1/(slew rate2)} for example: if slew rate 1 is 0.5 v/ns and slew ra te 2 is 0.4 v/ns, then the delta rise, fall rate is -0.5 ns/v. using the table given, this woul d result in the need for an increase in t ds and t dh of 100 ps. k. table 3 is used to increase t ds and t dh in the case where the i/o slew rate is below 0.5 v/ns. the i/o slew rate is based on the lesser of the ac-a c slew rate and the dc-dc slew rate. the input slew rate is based on the lesser of the slew rates determined by either v ih(ac) to v il(ac) or v ih(dc) to v il(dc) , and similarly for rising transitions. m. dqs, dm, and dq input slew rate is specifi ed to prevent double clocking of data and preserve setup and hold times. signal transitions through the dc region must be monotonic. www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 34 - revision a01 11. timing waveforms 11.1 command input timing 11.2 timing of the clk signals www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 35 - revision a01 11.3 read timing (burst length = 4) t is t ih da0 da1 da2 t ch t cl t ck add cmd clk clk read col qa0 qa1 qa2 da3 qa3 t rpre t dqsck t dqsck t dqsck t rpst postamble preamble hi-z hi-z t dqsq t dqsq t dqsq t qh t qh t ac t lz t hz hi-z hi-z da0 da1 da2 qa0 qa1 qa2 da3 qa3 t rpre t dqsck t dqsck t dqsck t rpst postamble preamble hi-z hi-z t dqsq t dqsq t dqsq t qh t qh t ac t lz t hz hi-z hi-z cas latency = 2 dqs output (data) cas latency = 3 dqs output (data) t is t ih notes: the correspondence of ldqs, udqs to dq. (W9425G6JH) ldqs dq0~7 udqs dq8~15 www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 36 - revision a01 11.4 write timing (burst length = 4) t is t ih t dsh t dss t dss t dsh t wpres t dh t dh t dh t ds t ds t ds t dqss t dsh t dsh t dss t dss postamble t wpre preamble t dqsh t dqsh t dqsl t wpst da 0 da1 da 2 da 3 t wpres t ds t ds t dqss t dsh t dsh t dss t dss postamble t wpre preamble t dqsh t dqsh t dqsl t wpst t wpres t dh t ds t ds t dqss postamble t wpre preamble t dqsh t dqsh t dqsl t wpst da 0 da 1 da 2 da 3 t ds t dh t dh t ch t cl t ck dqs input (data) ldqs dq0~7 udqs dq8~15 x4, x8 device x16 device add cmd clk clk writ col da0 da1 da2 da3 da0 da1 da2 da3 t dh t dh t dh t ds da 0 da 1 da 2 da 3 da0 da1 da2 da3 t is t ih note: x16 has two dqss (udqs for upper byte and ldqs for lower byte). even if one of the 2 bytes is not used, both udqs and ldqs must be toggled. www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 37 - revision a01 11.5 dm, data mask (W9425G6JH) www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 38 - revision a01 11.6 mode register set (mrs) timing mrs register set data next cmd t mrd clk clk cmd add a2 a1 a0 a3 a6 a5 a4 a8 ba1 ba0 000 000 001 010 011 100 101 110 111 001 010 011 100 101 110 111 0 1 0 1 1 1 0 0 0 1 0 1 2 4 8 2 4 8 burst length sequential interleaved reserved reserved reserved reserved reserved reserved sequential interleaved addressing mode cas latency 2 dll reset no yes mrs or emrs regular mrs cycle extended mrs cycle 2.5 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 ba0 ba1 "0" "0" "0" "0" "0" "0" "0" dll reset reserved addressing mode * "reserved" should stay "0" during mrs cycle. reserved mode register set or extended mode register set cas latency burst length reserved reserved 3 4 www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 39 - revision a01 11.7 extend mode register set (emrs) timing emrs register set data next cmd t mrd a0 ba1 ba0 0 1 0 1 0 1 enable disable dll switch mrs or emrs regular mrs cycle extended mrs cycle a0 a1 a2 a3 a4 buffer strength dll switch reserved a6 a1 1 1 0 0 buffer strength 100% strength 60% strength 30% strength reserved buffer strength reserved * reserved should stay 0 during emrs cycle mode register set or extended mode register set cmd add clk clk 0 1 0 1 1 1 0 0 a5 a6 a7 a8 a9 a10 a11 ba0 ba1 " 0 " " 0 " " 0 " " 0 " " 0 " " 0 " " 0 " " 0 " " 0 " " 0 " " 0 " a12 " 0 " www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 40 - revision a01 11.8 auto-precharge timing (read cycle, cl = 2) 1) t rcd (reada) t ras (min) ? (bl/2) t ck ap q7 q6 q5 q4 q3 q2 q1 q0 act reada act q0 q1 q2 q3 act reada act q0 q1 act ap reada act t rp t ras cmd dqs dq cmd dqs dq cmd dqs dq bl=2 bl=4 bl=8 clk clk ap notes: cl=2 shown; same command operation timing with cl = 2,5 and cl=3 in this case, the internal precharge operation begin after bl/2 cycle from reada command. ap represents the start of internal precharging. the read with auto-precharge command cannot be interrupted by any other command. www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 41 - revision a01 11.9 auto-precharge timing (read cycle, cl = 2), continued 2) t rcd/rap(min) t rcd (reada) < t ras (min) ? (bl/2) t ck ap q7 q6 q5 q4 q3 q2 q1 q0 act reada act q0 q1 q2 q3 act reada act q0 q1 act ap reada act t rp t ras cmd dqs dq cmd dqs dq cmd dqs dq bl=2 bl=4 bl=8 clk clk ap t rap t rcd t rap t rcd t rap t rcd notes: cl2 shown; same command operation timing with cl = 2.5, cl=3. in this case, the internal precharge operation does not begin until after t ras (min) has command. ap represents the start of internal precharging. the read with auto-precharge command cannot be interrupted by any other command. www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 42 - revision a01 11.10 auto-precharge timing (write cycle) ap act act writa act writa cmd dqs dq cmd dqs dq cmd dqs dq bl=2 bl=4 bl=8 clk clk ap ap d0 d1 d0 d1 d2 d3 d0 d1 d2 d3 d4 d5 d6 d7 t dal t dal t dal writa the write with auto-precharge command cannot be interrupted by any other command. ap represents the start of internal precharging. www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 43 - revision a01 11.11 read interrupted by read (cl = 2, bl = 2, 4, 8) 11.12 burst read stop (bl = 8) www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 44 - revision a01 11.13 read interrupted by write & bst (bl = 8) burst read cycle must be terminated by bst command to avoid i/o conflict. 11.14 read interrupted by precharge (bl = 8) read cmd dqs dq clk clk pre q0 q1 q2 q3 q4 q5 q0 q1 q2 q3 q4 q5 cas latency cas latency cas latency = 2 dqs dq cas latency = 3 www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 45 - revision a01 11.15 write interrupted by write (bl = 2, 4, 8) 11.16 write interrupted by read (cl = 2, bl = 8) writ cmd dqs dm clk clk t wtr dq d4 d5 d6 d7 d0 d1 d2 d3 data must be masked by dm read data masked by read command, dqs input ignored. q4 q5 q6 q7 q0 q1 q2 q3 www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 46 - revision a01 11.17 write interrupted by read (cl = 3, bl = 4) writ cmd dqs dm clk clk read t wtr dq q0 q1 q2 q3 d0 d1 d2 d3 data must be masked by dm 11.18 write interrupted by precharge (bl = 8) writ cmd dqs dm clk clk act t wr dq d4 d5 d6 d7 d0 d1 d2 d3 data must be masked by dm pre t rp data masked by pre command, dqs input ignored. www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 47 - revision a01 11.19 2 bank interleave read operation (cl = 2, bl = 2) cmd dqs clk clk dq q0a q1a q0b q1b acta/b : bank act. cmd of bank a/b readaa/b : read with au to pre.cmd of bank a/b apa/b : auto pre. of bank a/b acta actb readaa acta readab actb apa apb t rcd(a) t ras(a) t rp(a) t ras(b) t rcd(b) t rp(b) cl(a) cl(b) preamble postamble preamble postamble t rrd trc(a) t rc(b) t rrd 11.20 2 bank interleave read operation (cl = 2, bl = 4) cmd dqs clk clk dq q2a q3a q2b q3b acta/b : bank act. cmd of bank a/b readaa/b : read with auto pre.cmd of bank a/b apa/b : auto pre. of bank a/b acta readaa actb readab acta actb apa apb trcd(a) tras(a) trp(a) tras(b) trcd(b) trp(b) cl(a) cl(b) preamble postamble trrd trc(a) trc(b) trrd q0a q1a q0b q1b www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 48 - revision a01 11.21 4 bank interleave read operation (cl = 2, bl = 2) cmd dqs clk clk dq q0a q1a q0b q1b acta/b/c/d : bank act. cmd of bank a/b/c/d readaa/b/c/d : read with auto pre.cmd of bank a/b/c/d apa/b/c/d : auto pre. of bank a/b/c/d acta actb readaa actc readab actd readac acta apa apb trcd(a) t ras(a) t rp t ras(b) t rcd(b) cl(a) cl(b) preamble postamble preamble t rrd t rc(a) t rrd t ras(c) t ras(d) t rcd(d) t rcd(c) t rrd t rrd 11.22 4 bank interleave read operation (cl = 2, bl = 4) www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 49 - revision a01 11.23 auto refresh cycle note: cke has to be kept ?high? level for auto-refresh cycle. 11.24 precharged/active power down mode entry and exit timing note: 1. if power down occurs when all banks are idle, this mode is referred to as precharge power down. 2. if power down occurs when there is a row active in any bank, this mode is referred to as active power down. 11.25 input clock frequency change during precharge power down mode timing nop nop nop dll reset nop nop cmd 200 clocks t is frequency change occurs here minmum 2 clocks required before changing frequency stable new clock before power down exit clk clk cmd cke t rp www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 50 - revision a01 11.26 self refresh entry and exit timing note: if the clock frequency is changed during self re fresh mode, a dll reset is required upon exit. www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 51 - revision a01 12. package specification 12.1 tsop 66 li ? 400 mil l1 o 1 o d 1 o o l e e1 www.datasheet.co.kr datasheet pdf - http://www..net/
W9425G6JH publication release date: may 26, 2010 - 52 - revision a01 13. revision history version date page description a01 may 26, 2010 all initial formally data sheet important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surg ical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales. www.datasheet.co.kr datasheet pdf - http://www..net/

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